Field of the Invention
The invention relates to a frequency-compensated, multistage amplifier configuration and to a method for operating a frequency-compensated amplifier configuration.
It is a conventional practice to use chopper amplifiers for offset-free, low-drift amplification of low-frequency signals. Such amplification involves the useful signal that is to be amplified by the amplifier having a chopper frequency applied to it both at the input and at the output. The input of the amplifier, accordingly, has a chopped useful signal applied to it that is amplified and is demodulated at the output of the amplifier with the correct phase. In such a case, the chopper signal is normally a square-wave signal.
Such a chopper amplifier is described, by way of example, in Enz et al.: xe2x80x9cA CMOS Chopper Amplifierxe2x80x9d, IEEE Journal of Solid-State Circuits Vol. SC-22, No 3, June 1987 pp. 335-341. However, spikes arise in this case. Filter measures are used to attempt to eliminate the effects thereof on the residual offset.
Japanese Patent document 59-224906 A specifies a chopper amplifier in which switched capacitors are provided to reduce stray capacitances in a negative feedback loop.
In addition, switched-capacitor circuits exist in which cyclic switching and charge reversal in capacitors, likewise, result in the amplifier output producing a square-wave voltage of high amplitude that has the useful signal superimposed on it.
A drawback of these circuits is that stray capacitances in the amplifier and load capacitances at the output result in the output signal from the amplifier lagging behind its input signal. To compensate for these phase shifts that arise at high frequencies, which are disadvantageous particularly when a plurality of amplifier stages are disposed in series and, as a result, an amplifier configuration can become unstable, it is conventional to use frequency compensation capacitors, xe2x80x9cMiller capacitors,xe2x80x9d which attenuate the gain at high frequencies. In such a context, the stability of the amplifier is achieved by reducing the gain-bandwidth product (GBW).
With chopped amplifier operation, the frequency compensation capacitors need to undergo charge reversal for every state change in the chopper signal. This has the drawback that sensitive measurement amplifiers and a given analog bandwidth and accuracy allow only low chopper frequencies to be produced. A low chopper frequency results in poor noise properties as a result of flicker effects and in higher signal delay times in the sampling amplifier.
Even designing the most broadband and fastest amplifiers possible that allow high chopper frequencies is disadvantageous on account of the relatively high power consumption and the relatively large amount of chip area required. In addition, a relatively high level of thermal noise is produced as a result of the relatively high gain-bandwidth product.
U.S. Pat. No. 5,621,319 to Bilotti et al. discloses a method for compensating for the directional offset voltage that is normally produced with Hall sensors. In such a case, the exciter current from the Hall sensor is cyclically switched between two terminal pairs for supplying the exciter current that are disposed at right angles to one another, while the Hall voltage can be picked off on the respective other terminal pair. This produces a similar problem to that with the chopper amplifier described because a chopped output signal from the Hall sensor needs to be amplified. With the chopped Hall principle too, the amplified, modulated signal is demodulated with the correct phase at the amplifier output, for example, by integration, with the offset voltage being largely eliminated on average over time.
The document xe2x80x9cSpinning-current method for offset reduction in Silicon Hall platesxe2x80x9d by Peter Jan Adriaan Munter, Delft University Press 1992, page 12 likewise specifies a Hall element that is operated in chopped mode and in which the Hall sensor has a multiplicity of connections that are interchanged cyclically, the Hall voltage respectively being able to be picked off on a terminal pair that is disposed at right angles to the terminal pair for the exciter current.
All the chopper amplifiers described have the common drawback that either high gain factors can be produced for a low chopper frequency and, hence, also for a low analog bandwidth, or relatively high bandwidths can be produced only with lower gains and with high power loss, that a large chip area is required and that they have poor noise properties.
It is accordingly an object of the invention to provide a frequency-compensated, multistage amplifier configuration, and method for operating a frequency-compensated amplifier configuration that overcome the hereinafore-mentioned disadvantages of the heretofore-known devices and methods of this general type and that allows large gain bandwidths to be produced for a small chip area requirement and has a low power consumption, a low noise, and high levels of accuracy and stability.
With the foregoing and other objects in view, there is provided, in accordance with the invention, a frequency-compensated, multistage amplifier configuration, including an input amplifier stage having an input and an output, an output amplifier stage having an input connected to the output of the input amplifier stage and output, a modulator connected to the input of the input amplifier stage, the modulator supplying the input amplifier stage with a useful signal chopped into a first and a second clock phase, a first Miller compensation capacitor electrically activatable between the input of the output amplifier stage and the output of the output amplifier stage during the first clock phase, and a second Miller compensation capacitor electrically activatable between the input of the output amplifier stage and the output of the output amplifier stage during the second clock phase.
In line with the invention, the Miller compensation capacitor used for an amplifier in the output stage needs to be provided in duplicate so that, when a chopped input signal is supplied, the first capacitor is active during a first clock phase and the second capacitor is active during a second clock phase. Such a configuration avoids the need for cyclic charge reversal in the compensation capacitor. This is so because, after just a few clock cycles, both the first capacitor and the second capacitor are charged and in further clock cycles follow only the small voltage differences that are caused by the useful signal and that have smaller amplitudes and are slower as compared with the voltage differences caused by the chopper clock frequency.
The amplifier, therefore, allows continuous-time signal processing, in contrast to switched capacitor filters operating based upon the sample-and-hold principle.
In a chopper amplifier, the first and second clock phases differ by virtue of the useful signal having a square-wave function of high amplitude superimposed on it so that the useful signal is available in uninverted form during the first clock phase and is available in inverted form during the second clock phase.
Alternatively, the useful signal can be chopped so that the amplifier can be supplied with the useful signal unchanged during one clock.phase and with an offset equalization signal during another clock phase.
The present principle avoids cyclic charge reversal in Miller or compensation capacitors in the frequency-compensated amplifier.
The basic advantage of the configuration described, therefore, has its basis in that, when dimensioning the amplifier, it is no longer necessary to take into account the requirements in the frequency range of the chopper clock frequency, but, instead, constructing the amplifier involves taking into account the actual useful signal bandwidth, which is usually much lower than the chopper frequency. Such a process allows the amplifier to be produced with a small chip area and low power loss with a high level of accuracy and low noise, while in the prior art compensation capacitor configuration the output signal""s transient recovery time, after which the output signal differs from a steady-state final value by only 0.1%, for example, is       ln    ⁢          xe2x80x83        ⁢                  10        3            ·              A                  G          ⁢                      xe2x80x83                    ⁢          B          ⁢                      xe2x80x83                    ⁢          W                      ;
where A=gain of the amplifier with feedback and GBW=gain-bandwidth product of the amplifier. With the shown principle of switched compensation capacitors, this transient recovery time is reduced approximately by a factor of 10. Because the respective valid compensation capacitor still stores the output voltage from the previous, corresponding clock phase, the amplifier at the input now needs to react to much smaller changes in the voltage. Hence, the change in the voltage value that the amplifier sees is only a small voltage change caused by the comparatively low-frequency useful signal. The advantage attained is particularly clear at high gain and when the amplifier has high accuracy requirements.
The frequency-compensated amplifier configuration can have more than two clock phases. This makes it suitable not only for Hall elements operated in chopped mode but also for Hall elements that operate based upon the spinning current principle.
The modulator can be an input changeover switch.
With multistage amplifiers, frequency compensation is, therefore, particularly important because it is necessary to avoid an unstable response from the amplifier configuration at high frequencies. This is because, with two series-connected amplifiers, the phase shift between the input and output can be up to 180xc2x0, which means that the normally negative feedback changes into positive feedback for the amplifier, resulting in instability. To avoid this, Miller capacitors or compensation capacitors are used. In such a case, frequency compensation is provided on the output-side amplifier stage, for example, in an operational amplifier having a plurality of amplifier stages.
In accordance with another feature of the invention, the output of a demodulator is connected to the frequency-compensated amplifier. The demodulator can be an output changeover switch or an output sample switch. To demodulate the amplified useful signal, the demodulator can have a clock signal applied to it that corresponds to that clock signal that can be supplied to the modulator or that is derived therefrom.
In accordance with a further feature of the invention, there is provided a demodulator connected to the output of the output amplifier stage, the demodulator demodulating an amplified version of the signal.
In accordance with an added feature of the invention, there is provided a demodulator connected to the output of the output amplifier stage, the demodulator demodulating a signal at the output of the output amplifier stage.
In accordance with an additional feature of the invention, the capacitance values of the first and second compensation capacitors are substantially equal and/or the same. This permits a particularly simple and symmetrical circuit design.
When the principle is applied to switched-capacitor amplifiers, however, the different gains of the configuration in the two clock phases can mean that it is advantageous for the compensation capacitors to be in asymmetrical form.
In accordance with yet another feature of the invention, to switch the compensation capacitors, a changeover switch is connected to the input of the output amplifier stage and to the capacitors whose outputs are connected to the amplifier. This changeover switch alternately connects the first or second compensation capacitor, depending on clock phase. The configuration of the switch upstream of the compensation capacitors has the advantage that switching transistors can be produced more easily on account of the defined potential levels that are at the amplifier input.
The useful signal can be in the form of a signal that is routed using differential-path technology, for example, for suppressing common-mode interference.
When designing circuits implementing the present principle, it should be remembered that simultaneous activation of the first and second compensation capacitors needs to be avoided in every operating state. By way of example, compensation capacitors can be turned on with a time delay and can actually be turned off before a change of clock phase so that there is never any overlap between the switching states. In such a case, in one advantageous embodiment of the invention, holding capacitors can be provided that are grounded at the input of the amplifier.
The invention can also be used for switched-capacitor amplifier circuits in which, during the first clock phase, the useful signal is supplied to the amplifier and, during the second clock phase, the supply of the useful signal is interrupted and an offset equalization signal is supplied.
In accordance with yet a further feature of the invention, the changeover switch for switching the first and second Miller compensation capacitors is an analog circuit with CMOS transistors.
In accordance with yet an added feature of the invention, the changeover switch for switching the first and second Miller compensation capacitors is an analog circuit with CMOS transistors.
In accordance with yet an additional feature of the invention, the signal is a differential signal.
It is within the scope of the invention for a single-stage amplifier configuration in a switched-capacitor filter to have at least one compensation capacitor grounded at the output of the frequency-compensated amplifier, which can be a transimpedance amplifier, instead of the configuration of the compensation capacitors between the input and the output of the amplifier.
It is also within the scope of the invention to provide switched compensation capacitors for multistage amplifiers, for example, three-stage or four-stage amplifiers. In such a case, the compensation capacitors can be disposed between the input and the output of the single amplifier stage and/or between the input and the output of a plurality of amplifier stages in the multistage amplifier. Combinations of switched and fixed compensation capacitors can, likewise, be appropriate.
In accordance with again another feature of the invention, there is provided a respective holding capacitor for signal lines carrying the differential signal between the modulator and the input amplifier stage, the respective holding capacitor being grounded.
In accordance with again a further feature of the invention, there are provided signal lines carrying the differential signal between the modulator and the input amplifier stage and a grounded holding capacitor connected to each of the signal lines.
In accordance with again an added feature of the invention, the modulator is a Hall sensor operated in chopped mode.
The invention can, advantageously, be used for Hall sensors operated in chopped mode in which the first and second clock phases of the modulated signal differ by the offset voltage of the Hall element.
In accordance with again an additional feature of the invention, the modulator is a chopped mode Hall sensor.
In accordance with still another feature of the invention, there is provided a demodulator connected to the output of the output amplifier stage, the demodulator demodulating a signal at the output of the output amplifier stage and having an integrator integrating the signal at the output of the output amplifier stage.
In accordance with still a further feature of the invention, the output amplifier stage is a frequency-compensated amplifier.
In accordance with still an added feature of the invention, the frequency-compensated amplifier is a switched-capacitor amplifier.
In accordance with still an additional feature of the invention, the frequency-compensated amplifier has an output and at least one of the first and second compensation capacitors is grounded at the output of the frequency-compensated amplifier.
With the objects of the invention in view, there is also provided a method for operating a frequency-compensated amplifier configuration, including the steps of providing an amplifier configuration having an amplifier with an input and an output and a modulator connected to the input of the amplifier, modulating a useful signal in the modulator to form two cyclically consecutive modulator clock phases, activating a first compensation capacitor between the input of the amplifier and the output of the amplifier during a first compensation clock phase, activating a second compensation capacitor between the input of the amplifier and the output of the amplifier during a second compensation clock phase, providing a respective no-overlap time between the first and second compensation clock phases during which neither the first compensation capacitor nor the second compensation capacitor is switched on. According to the invention, a respective no-overlap time is observed during which neither the first nor the second compensation capacitor is connected between the first and second compensation clock phases.
The timing scheme described for operating an amplifier configuration has the advantage that the first and second compensation capacitors are never simultaneously active between amplifier input and amplifier output.
In accordance with another mode of the invention, the start of the modulator clock phases, respectively, comes in the no-overlap time between the first and second compensation clock phases. Specifically, a start of the first modulator clock phase comes in the no-overlap time between the second and first compensation clock phases and a start of the second modulator clock phase comes in the no-overlap time between the first and second compensation clock phases.
In accordance with a further mode of the invention, the demodulation downstream of the amplifier takes place such that no state change in a functional unit connected upstream of the demodulator takes place during the demodulator clock phases. This largely avoids spikes in the output signal that can be derived on the demodulator.
In accordance with a concomitant mode of the invention, the amplifier is a frequency-compensated amplifier and an amplified version of the useful signal is demodulated with a demodulator connected downstream of the frequency-compensated amplifier such that the amplified useful signal can be derived at the output of the frequency-compensated amplifier unchanged during a first demodulator clock phase and in an inverted form during a second demodulator clock phase, the first demodulator clock phase starting after the start of the first compensation clock phase and ending before an end of the first modulator clock phase, and the second demodulator clock phase starting after the start of the second compensation clock phase and ending before an end of the second modulator clock phase.
Other features that are considered as characteristic for the invention are set forth in the appended claims.
Although the invention is illustrated and described herein as embodied in a frequency-compensated, multistage amplifier configuration, and method for operating a frequency-compensated amplifier configuration, it is, nevertheless, not intended to be limited to the details shown because various modifications and structural changes may be made therein without departing from the spirit of the invention and within the scope and range of equivalents of the claims.